The ConfigData family of classes read the configuration data from the configuration file and store the values. There are two classes based on ConfigData:
- BankData
- ModeData
BankData stores values read from a specific BANK section of the configuration file (bank dependent), and serve to configure each individual bank, with bank-specific data such as IP addresses, etc. For example: if a Player is controlling Bank A, it will read and record the configuration data from section [BANKA] in the configuration file.
ModeData stores values read from the MODE sections of the configuration file. All modes are used by all backends, depending on instrument configuration.
A common base class for data read out of a config file using ConfigParser. It’s main purpose is to serve as a common area for helper functions.
get_bool(section, key)
Returns a boolean value, or None if that is not possible. The value in the config file should be one of ‘true’|’false’ (of any character case combination of this), or 0 or 1.
get_float(section, key)
Returns a value of type float, or None if that is not possible.
get_int(section, key)
Returns a value of type int, or None if that is not possible.
Returns a vector of ints from ‘key’.
get_string(section, key)
Returns a value of type string, or None if that is not possible. The string is cleaned up: leading and trailing ‘”’ characters and whitespaces are removed.
Helper function that looks for ‘key’ in ‘config’ and returns the requested value as type ‘val_type’, or None if that is not possible or the key or value doesn’t exist.
returns: A dictionary of kv pairs, empty if kvkey is not there, or if it doesn’t have any value, or if any of the values are not themselves keys in the section.
Looks in the ConfigParser object for a key-of-keys kvkey which list a set of arbitrary keys to be read that the program does not know about. The value associated with this key is a comma delimited list of keys. The function parses this, then iterates over the keys to obtain the values, returning a dictionary of key/value pairs. Given an entry in a configuration file’s section [MODE1] as follows:
shmkeys = foo,bar,baz
foo = frog
bar = cat
baz = dog
then:
cf.read_kv_pairs(config, 'MODE1', 'shmkeys')
-> {'bar': 'cat', 'baz': 'dog', 'foo': 'frog'}
These may then be used in any way by the Player code. One use, as implied in this example, is to store these values in shared status memory. Another use is to read register/value pairs to be directly written to the FPGA.
Container for all Bank specific data.
Given a comma delimited string of filter bandwidh kv pairs, creates a dictionary with the filter_bw as a key and the I2C bits for that filter_bw as a value.
The 10Gbs IP address for the roach
The 10Gbs port for the roach
The 10Gbs HPC IP address
The KATCP host, on the 1Gbs network
whether this bank controls a roach or not.
The host name of the HPC computer hosting the Player
Switching Signals master flag. True if this bank is the master.
The KATCP host, on the 1Gbs network
The KATCP port on the 1Gbs network
Given the open ConfigFile object config, loads data for bank. config normally is opened with the config file at $DIBAS_DIR/etc/config/dibas.conf
The base mac address used to compute individual mac addresses for the roaches.
The bank name
The port number for the Player, used by the Dealer interface
Arbitrary FPGA register key/value pairs. Read from the config file and written directly to the FPGA.
Arbitrary shared memory key/value pairs. Read from the config file and placed in shared status memory.
The location of the Valon serial port: ‘katcp’ (on roach) or ‘local’ (on hpc machine)
List of Valon options. With the exception of the reference frequency multiplier, all of these are flags which either are clear (0) or set (1): doubler, halver, multiplier, low-spur
The Valon serial port device (i.e. /dev/ttyS1)
The reference frequency: ‘internal’ or ‘external’
The frequency of the Valon’s external reference
The Valon RF level, in dBm. Legal values are -4, -1, 2, and 5
Valon VCO range
Container for all Mode specific data.
Sequence of FPGA register writes necessary to arm the ROACH.
Name of the backend type. This is used to determine which Backend to instantiate. May be one of:
h1k, h16k l1/lbw1, l8/lbw1, l8/lbw8, guppi-inco, guppi-codd
BOF file for this mode
The IP addresses of the HPC computers that are the end-points for each the CoDD ROACH’s network adapters. There are 8 of these.
In CoDD mode, the HPC that will control the ROACH. Since theCoDD modes only use 1 ROACH but 8 HPC machines, one must be designated to be the controller.
Flag, whether this mode is a coherent de-dispersion mode.
The IP addresses of the onboard network adapter for the CoDD roach. The CoDD roach has 8 of these. This is a dictionary, keyed by bank name:
datahost = self.cdd_roach_ips[bankname]
Filter bandwidth
Valon frequency
Optional gain values for LBW modes. L1LBW1 and L8LBW1 only require on value. L8LBW8 require 8, as a vector.
The HPC DAQ program that will handle data for this mode: ‘vegas_hpc_server’, ‘guppi_daq_server’, etc.
Optional command-line parameters to pass into the hpc program specified.
Shortest possible integration, in seconds
Given the open ConfigFile object config, loads data for mode. config normally is opened with the config file at $DIBAS_DIR/etc/config/dibas.conf
This dictionary contains the master/slave select values.
The value chosen depends on whether the backend is master, what the switching signal source is (internal/external), and what the blanking source is (internal/external).
Typical config file entry:
0x00,0x00,0x00,0x0E,0x00,0x00
The order of the elements is as follows, where ‘m’ is master, ‘s’ is slave, ‘int’ is internal, and ‘ext’ is external:
m/int/int, m/int/ext, m/ext/ext, s/int/int, s/int/ext, s/ext/ext
A typical use would be: ssg_ms_sel = self.name.master_slave_sels[master][ss_source][bl_source] where:
Mode name
Number of channels, BOF specific value
The time needed by the backend to arm in this mode.
Sequence of FPGA register writes required post-arm.
Sequence of FPGA register writes necessary to reset the ROACH.
Arbitrary FPGA register/value pairs that are to be written to the FPGA for this mode.
BOF specific value
Arbitrary shared memory keys to be placed into status shared memory for this mode.