Direct Memory Access (DMA)

In order to minimize the workload of the computer's CPU, the A/D system is configured to use DMA services to store the acquired data. An AT class computer, such as the computer used in the ZY system, has 2 DMA controllers, one providing 8 bit DMA services on DMA channels 0-3, and the other providing 16 bit services on channels 5-7. Both will allow a maximum of 65,536 words. The ZY's A/D hardware is configured to use 16 bit DMA channel 5, and the software sets aside a 128 KByte DMA buffer to store the samples. To perform a measurement, the appropriate DMA controller is preloaded with the total number of samples desired, and is then given a software trigger. The A/D system then synchronizes with the IF reference, and takes samples until the DMA terminal count is reached. As an example, consider a measurement made with the ZY's default cycle and samples-per-cycle values. The measurement will integrate over 128 cycles, with 64 samples per cycle, and the number of 16 bit words in the DMA buffer will total 8192. The DMA buffer can now be thought of either as an array of 8192 individual 16 bit samples, or as an array of 128 structures, each structure representing a complete set of 64 samples of an IF cycle. The phase calculation algorithm treats the buffer as the latter.