Data Acquisition System

The ZY uses DMA driven data acquisition. The conversions are triggered by an external trigger and are clocked by an external clock. The conversions are then stored by the embedded PC's DMA controller directly into memory within a DMA buffer area. The ZY uses an 8254 programmable counter-timer located on board the DAQ16 to generate both of these signals, as well as the reference signal that these signals are phase locked to. Because the object of the ZY is to measure the phase of the modulated laser beam returned by a retroreflector target, the ZY's A/D interface is presented in terms of this signal: The number of cycles of this signal to integrate (CYC), the number of samples-per-cycle to acquire (SFQ), and the frequency of the cycles (IFF). These are then internally converted to the parameters that the A/D system needs to begin the conversion process: the frequency of the external sampling clock, and the terminal count for the DMA controller, as follows:

$$f_{CLK} = n \times f_{REF}$$ (2.1)

$$C_{term} = n \times m$$ (2.2)

where:

$$\begin{eqnarray*} f_{CLK} & = & {\rm The\ sampling\ clock\ frequency}\\ n &... ...\ m & = & {\rm The\ number\ of\ cycles\ in\ a\ measurement.} \end{eqnarray*}$$

The A/D system does have physical limits. Because of the A/D converter used, $f_{CLK}$ cannot exceed 100 kHz. Further, the embedded PC imposes a limit of 65536 samples on $C_{term}$, because the DMA controller's registers are 16 bit registers. Since these are limits on the underlying A/D parameters, and not the interface parameters used to create them, it is the combination of interface parameters that can lead to trouble. For example, a value for $n$ that is legal when $m=1000$ may not be legal at $m=2000$. The CYC, SFQ and IFF commands will therefore trap any values entered that cannot coexist with other parameters currently in use. The A/D is handled by class DAQ16. The PC's DMA controller is handled by class DMA16. The class Phase_M uses objects of these two classes to set up the DMA buffers required, set the DMA controller to the proper mode for the acquisition of the required number of samples, set up the DAQ16's 8154 counter timer to provide the proper reference frequency and sampling frequency, and finally to trigger a data acquisition. The ZY performs a measurement as follows (see figure 2.8):

1. The external A/D conversion clock is set to the correct frequency
2. The DMA terminal count is loaded in the DMA controller
3. The DAQ16 A/D converter is ``armed'' by loading a command word that controls its operation. This control word sets the A/D converter to use an external trigger, external conversion clock, use DMA conversion etc.
4. The trigger pulse is generated (under software command) as follows:
   1. DAQ16::trigger() is called
   2. trigger() waits for the reference signal to go high.
   3. trigger() waits for the reference signal to go low.
   4. trigger() loads the clock, programming it to deliver a one-shot pulse when the reference signal goes high again. The trigger pulse occurs on the next rising edge of the reference signal. Because of the relationship between the clock signals, the first conversion will occur on the first conversion clock pulse following the trigger (not the one right on top of the conversion trigger).
5. On end of conversion, the ZY calculates phase and amplitude information from the data.

The ZY performs steps 1 and 2 only when the relevant measurement parameters change. The remaining steps are performed by the ZY every time a conversion is made. Immediately after triggering a conversion, Phase_M acquires a time stamp from the bc630AT object. Once the DAQ16 is triggered, it will acquire data and place it in the DMA buffer, using the DMA controller, until the terminal count is reached. At this point, the DAQ16 signals end-of-acquisition. This data represents samples from a number of laser modulation cycles all in sequence. Phase_M then uses one of three routines to reduce this data. Two of the routines will sum up all related data points from each cycle before taking their sine and cosine components and summing them up. In other words, sample one of cycle one is summed with sample one of cycle 2, and sample 1 of cycle 3, etc., until all samples one of every cycle are summed. Then sample 2 of cycle 1 is summed to sample 2 of cycle 2 etc.

Figure 2.8: A/D System Timing Diagram.

Once sine and cosine sums are obtained, phase and amplitude can be derived from these (See reference [8]). The third routine calculates sine and cosine sums (and thus phase and amplitude) for each discrete cycle in the sequence of data. This routine, and one of the previous two, have been extensively optimized in hand coded assembly language. This has resulted in a five fold increase in processing speed for the cycle integrating optimized function, and a two fold increase in processing speed for the cycle sequence calculating function.