Caltech Continuum Backend Videocon Monday 07jul03 present: Tim Pearson, Tony Readhead, Martin Shepherd, Phil Jewell, Brian Mason, John Ford, Galen Watts, Rich Lacasse, Roger Norrod Background: We held the videocon in order to provide feedback on a number of specific issues that Caltech had raised now that they are getting on with the hardware design. The main issues were: the overall architecture change (to a faster, lower-resolution ADC further up in the signal chain, followed by low pass filters and integrating in subsequent FPGAs); cabling, wiring, and connectorization strategy. Roger points out that if we're sampling at 100ns (new scheme) then the time constant of the post-detector video amps must be fast ("fast" meaning the step response of 1 usec, or a few MHz bandwidth). However the slew times of the post detector op-amps certainly limited WMAP's switching rate-- perhaps we can use better components than them. Clarifying our earlier definition of "fast" we said the step response should be 0.5 usec, settling to -84dB at 1 usec (-84 dB is a part in 4000 that is, 12 bits). Generally the properties of this circuit may be key and the circuit is as yet undesigned; GB should have someone look at a design and Spice simulations soon, but indicated that it is ok for Caltech to plan on us meeting this spec. GB also indicated that it was acceptable and sensible to plan on putting video filters on our side of the interface, probably in the Rx before the wiring/connectors running between Rx and Backend. Brian indicated that 1 usec blanking out of 25 usec is acceptable and we don't need to push too hard to reduce this (although if feasily feasible that's obviously good). Rich stated a rule of thumb that we have for our backends which I didn't quite get down clearly (the signal is down by 15 dB at the nyquist frequency, which results in aliased signal being 30 dB down?)-- and wonders whether the aliased stuff is signal or noise (worst case: some sort of systematic noise which doesn't average down). The full-scale voltage of the ADC being considered is 2.5 Volts. We indicated to Caltech that from our point of view, the signal levels are open to specification by them. The ADC is clocked at 10 MHz (5xNyquist). In response to Martin's query about the detector noise budget, we decided that it was fair to assume that the noise budget is dominated by the receiver. We decided that differentially driven, individually shielded, twisted pairs were good for the analog signals. The Skewclear cables Martin has found look sensible. These are D-connector-izable. Since the signals are differential crosstalk will be lower; video filters in the receiver will also reduce the crosstalk. Discussion of the control signals was somewhat less conclusive. Will we use LVDS or TTL? Not clear, although we think that either could be used. We currently use mostly TTL although this needn't be a constraint as there will simply be a multiplexer/lockout card that both (CCB and switching signal generator) signals feed into for the receiver. Are both TTL and LVDS compatible with using the opto isolators? Not clear. How fast can the opto-isolators be driven? Martin will look into the last question. We also need to clearly determine the bandwidth required for them. Brian claims that according to our initial design & specifications no individual component in the receiver is toggled faster than every 50 usec. The backend may allow driving all the switches every 25 usec but there is no intent to do this (intent is to drive them alternately). The specific bandwidth requirement then depends on how the control signals are combined and sent. A sketch of the control signals would be helpful and GB will produce this. It should be kept in mind that the 3mm Rx has half as many phase switches (2 not 4), and half as many cal diodes (1 not 2), as the 1cm Rx. As to interconnection: the general feeling was that more connectors rather than fewer was good: this permits empirically optimizing the grounding and bundling scheme, and presents more options for troubleshooting should they be needed. The specifics of whether we have four bundles of four cables each, or 16 individual cables, is open, and probably not critical. It should be kept in mind that the 3mm Rx has 12 not 16 detectors (3 groups of 4, not 4 groups of 4). Galen asked if the phase switches and cal diodes will be driven directly by the backend, and they will. Tony readhead inquired as to the front end schedule. Galen Watts is hard at work on the receiver and we plan to have it ready in the lab by 01jan04. Tony also requested that if possible we get back to them within a month or two on the software which has been delivered; and indicated that it would be sensible to have someone from JPL participate in the CCB CDR since our current efforts have some overlap with the 91 element MMIC array under development. Martin asked if we have some video filters lying around which we could have a quick look at. We do, and we might be able to have a look at them; failing that we could probably give some pointers. We will touch base in a week or two to see when is a good time for the next videocon. Summary of Actions ================== *Martin: check opto isolator bandwidth. *???: look at post detector circuit design. *Galen: sketch control signals for 1cm Rx. Run this by Mike for obvious deltas to 3mm. *Rich: see if we have a representative video filter lying around and do a test or send Caltech the part number (or the part). *Brian: follow up on software with GB software development division.